As central processing units (CPUs) continue to get faster, the memory units that supply the data to the CPUs must continually get faster as well. In a typical computer system, a variety of different memory devices are employed to meet the needs of a particular application, wherein each memory device provides a trade-off in storage capacity, cost and response time. System performance is maximized by utilizing the devices in a hierarchy arrangement, utilizing both extremely fast, but low-capacity memory devices in combination with slower, higher capacity memory devices. The memory hierarchy would include both on-chip memory devices (e.g., processor registers, caches, etc.) as well as off-chip memory devices (e.g., main memory devices and disk storage). For example, a computer system may employ a hard disk drive (HDD) as the disk storage device and a dynamic random access memory (DRAM) as the main memory. The hard disk drive provides cheaper storage (i.e., cost/GB), and higher capacity, but slower response time. In contrast, the DRAM device provides faster response time, but at higher cost and lower capacity.
In recent years, non-volatile memory (NVM) devices in the form of solid-state drives have been employed as a complementary type of disk storage, used either instead of or in conjunction with a HDD. The NVM devices provide faster response time than a typical HDD, but at a slightly higher cost per gigabyte (GB). Both are located “off-board”, and therefore communicate with the CPU via a data bus. As such, HDD and NVM devices are often referred to as an “Input/Output (I/O) Memory Tier”, because they require input/output operations to communicate with the CPU.
Although a variety of data buses are available to provide communication between CPUs and SSD devices, the peripheral component interconnect express (PCIe) type data bus has emerged as a good candidate because of the throughput (e.g., 16 GB/s plus) capable of being provided. A communication interface known as NVM express (NVMe) has been proposed to enable host computer systems to communicate with SSD devices via a PCIe (or equivalent) bus. The interface provides an optimized command issue and completion path. Included in the NVMe interface is an “abort” command that allows commands issued by the host system to be aborted, rather than executed. However, issuance of the abort command according to the NVMe standard only addresses a small sub-set of possible scenarios. It would therefore be beneficial to develop an abort command that operates within the framework of the NVMe standard, but is applicable to a wider range of possible scenarios.